1. Field of the Invention
The present invention generally relates to the testing of integrated circuits (ICs) and circuit boards, or substrates, on which ICs are mounted and, more specifically, to a logic circuit for a circuit boundary scan cell and a method for performing parametric tests on a circuit having digital and analog pins.
2. Description of Related Art
As printed circuit boards populated with ICs get smaller and more dense, it becomes more difficult to quickly diagnose and repair the boards. As a result, digital boundary scan is becoming a popular design for test (DFT) technique to permit quick verification of board-level connections between ICs. Further, as the pin-count of new ICs increases each year, and the cost of high pin-count testers increases, it becomes necessary to consider reduced pin count testing where only a small subset of an IC's pins are contacted during an IC test. The un-contacted pins are then tested via boundary scan circuitry that controls every pin.
The preferred way, in industry, to implement digital boundary scan is according to the rules defined in the “IEEE Standard Test Access Port and Boundary-Scan Architecture”, published in 1990 and 2001, by the Institute for Electrical and Electronic Engineers (IEEE), which is also known as IEEE Std. 1149.1-2001, or simply 1149.1. This standard requires a minimum of one shift register bit per IC pin, and shifts boundary scan data in to a boundary scan register via a pin denoted TDI and out through a pin denoted TDO, as shown in FIG. 1. FIG. 1 shows a circuit 10 having digital circuitry 12 and digital pins 14. The shift register bits are implemented by means of boundary scan cells 16. A boundary scan cell for an individual digital pin is shown in FIG. 2. Boundary scan cell 16 includes a shift register element 18 whose output is connected to an update latch 20 and to a cell test data output TDO. A cell output multiplexer 22 receives a functional input, shown as “From core”, and the output of update latch 20 and a mode control signal, shown as selectJtagOut, and provides an output to pad 24 via pin driver 26. A cell input multiplexer 28 receives the output of mux 22 and a test data input TDI and a control input shown as ShiftEnable. A Test Access Port (TAP) controller 30 is provided to facilitate digital boundary scan testing. FIG. 1A is a state diagram for TAP controller 30.
A digital boundary scan test comprises enabling a serial shift register that accesses the pins of an IC, shifting in logic values to each output pin, updating the logic value at each output pin with the value shifted in, parallel capturing the logic values received at each input pin, and serially shifting out the captured values for examination by a tester.
Another standard entitled “IEEE Standard for a Mixed Signal Test Bus”, was published in 1999 by the IEEE, and is known as IEEE Std. 1149.4-1999, or simply 1149.4. The general architecture of an IC designed according to 1149.4 is shown in FIG. 3. FIG. 3 is similar to FIG. 1 except for the addition of analog circuitry 32 and a Test Bus Interface (TBIC) Circuit 34 which connects and controls internal buses AB1 and AB2 to external buses via pins AT1 and AT2 and analog boundary modules (ABM) 36 associated with analog pins 38. 1149.4 defines an analog bus that connects, within each IC, to the pins of the IC and permits an analog stimulus current to be conveyed to each pin on a bus, AB1, and the analog response voltage to be conveyed from each pin on another bus, AB2, as shown in FIG. 4. Electrical connection of each pin to each analog bus wire is enabled by two dedicated logic bits, denoted B1 and B2, of a boundary scan shift register (BSSR), according to 1149.4, and each on-chip analog bus Wire is also connected via the test bus interface circuit (TBIC) to an off-chip analog bus pin, AT1 or AT2, of the IC. This permits a stimulus signal to be supplied from a signal source external to the ICs and the response voltage to be measured by equipment external to the ICs. The digital state of each pin is also controlled by two dedicated bits, denoted D and C in FIG. 4, of the BSSR, according to 1149.4, for a total of four BSSR bits per pin.
The capabilities of this 1149.4 test bus have been described in several published papers, including, “Design, Fabrication, and Use of Mixed-Signal IC Testability Structures” by K. Parker et al, published in the Proceedings of the 1997 ITC (Nov. 1–6, 1997). This test bus was primarily designed to permit the measurement of discrete passive components, including capacitors and resistors, that are connected to the pins of ICs and that might otherwise be inaccessible due to the density of the circuit boards containing these ICs and components. It is possible to apply a stimulus to a pin, via one of these test buses, and to simultaneously monitor the pin's response voltage via another of these test buses, and to thus determine the impedance of a circuit that has been connected to the pin. The boundary scan cell for an individual analog pin is shown in FIG. 4. Almost identical circuitry is used for a digital pin if analog access to the pin is desired. It will be seen that an 1149.4 test cell requires many more gates than an 1149.1 test cell.
A paper entitled, “A Demonstration IC for the P1149.4 Mixed-Signal Test Standard” by K. Lofstrom and published in the 1996 ITC Proceedings (Oct. 20–25, 1996) discloses a technique denoted as “Early Capture” for comparing a pin voltage to a reference voltage that is supplied via one of the 1149.4 on-chip analog buses, and the digital comparison result is shifted out via the boundary scan register and TDO. A comparator is connected to the data scan register bit associated with each pin's signal.
Frodsham et al U.S. Pat. No. 6,262,585 granted on Jul. 17, 2001 for “Apparatus for I/O Leakage Self-test in an Integrated Circuit”, discloses circuitry which is the same as that prescribed by 1149.4, except that some elements have been removed, such as the second analog bus access to the pad. A boundary scan register bit at each pin enables an analog switch that connects an analog current stimulus bus to the pin. A comparator compares the voltage at the pin and an externally-supplied voltage threshold to determine if the leakage current through the pin is excessive.
Russell et al. U.S. Pat. No. 5,404,358 granted on Apr. 4, 1995 for “Boundary Scan Architecture Analog Extension” discloses a method and apparatus which provide an analog mode of operation of a standard test access bus interface based on a standard Boundary Scan architecture. Circuits are included in the interface which enable a sharing of data paths at separate time intervals defined under instruction control for processing analog and digital signals thereby providing a hybrid capability without any increase in the number of lines required by the interface.
Whetsel U.S. Pat. No. 5,744,949 granted on Apr. 28, 1998 for “Analog Test Cell Circuit” discloses analog test cells that permit testing analog circuitry.
Applicant's U.S. patent application Ser. No. 09/768,501 filed on Jan. 25, 2001 for “Method for Scan Controlled Sequential Sampling of Analog Circuits and Circuit for Use Therewith”, incorporated herein by reference, discloses the 1149.4 boundary scan cell to permit “partial updating”—updating only the latches that control the analog switches connecting each pin to the analog buses. This circuit requires a third mode signal to control whether full or partial update occurs.
A proposed standard for boundary scan testing of AC coupled differential signals, denoted as IEEE P1149.6 proposes comparing AC-coupled digital input signals to a reference voltage using a hysteretic comparator connected to each pin of a differential pair, and capturing the output of the comparator by the pin's boundary scan register bit, and then shifting out captured values via the boundary scan register. A hysteretic comparator is a comparator with hysteresis—its apparent input switching point is decreased slightly if the previous input voltage was higher than the reference voltage, and it is increased slightly if the previous input voltage was lower than the reference voltage.
A drawback of existing circuits is that a designer who wishes to provide analog access to digital IC pins that are controlled by 1149.1 boundary scan, is compelled to use the 1149.4 boundary scan cells of FIG. 4, and accept the accompanying gate count penalty, in order to use conventional 1149.1 and 1149.4 software and hardware tools for performing boundary scan testing.